Verigy 93k Tester Manual !exclusive! -

The Verigy 93000 (V93K) SoC Series is the semiconductor industry standard for Automated Test Equipment (ATE). Navigating its extensive documentation is essential for test engineers to maximize throughput, optimize multi-site efficiency, and debug complex mixed-signal, digital, and RF integrated circuits. 1. System Architecture and Hardware Overview

Understanding the physical architecture explained in the manual is vital for writing clean test programs and designing Load Boards (Device Interface Boards / DIBs).

Checks for open or short circuits on signal pins. The PPMU forces a small negative current (e.g., ) and measures the voltage drop. A reading between indicates a healthy protection diode. Leakage Testing (

The Verigy 93000 uses a software suite called SmarTest. It helps you write, run, and fix test programs. SmarTest 7 vs. SmarTest 8 verigy 93k tester manual

The test flow is the sequence in which individual test methods are executed. The manual covers:

): Evaluates input pin insulation. The tester forces a static voltage ( VDDcap V sub cap D cap D end-sub VSScap V sub cap S cap S end-sub

Within SmarTest, users can access documentation by selecting Help > Help Contents . The Verigy 93000 (V93K) SoC Series is the

The official documentation for the 93k system is vast, spanning thousands of pages split across distinct hardware and software manuals. If you are using the system, look for these specific document suites within your software installation directory (usually found under the doc or help folders of the SmarTest path). Hardware & Maintenance Manuals

Covers system infrastructure, including the different test head classes (A, C, S, and L), power supplies, and cooling systems. It includes procedures for docking loadboards and handling the test head.

: Lists standard C++ and Java methods used to program custom test steps, control instrumentation, and extract parametric data. Calibration and Maintenance Guides A reading between indicates a healthy protection diode

The digital subsystem operates on a "tester-per-pin" architecture. Each digital channel features independent timing generators, algorithmic pattern generators (APGs), and per-pin parametric measurement units (PPMUs).

The test head holds the electronic cards. It moves up and down to touch the chips on a wafer or package. It keeps the signals clean and fast. Support Infrastructure Chills the tester cards using liquid or air. Power Supplies: Delivers clean power to the system. Manipulator: Holds and moves the heavy test head. Hardware Configuration and Instrumentation